Reconfigurable logic circuits such as a field Programmable gate array (FPGA) achieve a predetermined logic (circuit configuration) based on data stored in a configuration memory.
In this case, configuration data for achieving the logic are referred to as a context. In recent years, as the increase in diversity of systems, multi-context reconfigurable logic circuits capable of storing a plurality of contexts and selectively achieving one of a plurality of logics have been suggested.
The multi-context reconfigurable logic circuit includes a plurality of contexts in a configuration memory having a plurality of memory devices. During operation of the logic circuit, contexts are preferably switched at a high speed.
However, in most cases, a logic circuit capable of switching contexts at a high speed is configured such that the configuration memory is made of SRAM (Static Random Access Memory). In this case, the area size of the SRAM is large, and therefore, as the number of contexts increases, there is a problem in that the configuration memory cannot be accommodated within a predetermined area in a chip.
Moreover, since the SRAM is volatile, contexts stored in the configuration memory are lost when the power is turned off. Therefore, there is a problem in that the SRAM based device cannot utilize a technique for turning off the power in the standby state in order to reduce power consumption. On the other hand, when the configuration memory is constituted by a nonvolatile memory device, there is a problem in that false writing is caused by a voltage continuously applied to the nonvolatile memory device during operation of the logic circuit (read disturb).